Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | /home/quang1806/Desktop/ACG525_TEST/ch26_hdmi_color (2)/src/color_bar.v /home/quang1806/Desktop/ACG525_TEST/ch26_hdmi_color (2)/src/dvi_encoder.v /home/quang1806/Desktop/ACG525_TEST/ch26_hdmi_color (2)/src/gowin_clkdiv/gowin_clkdiv.v /home/quang1806/Desktop/ACG525_TEST/ch26_hdmi_color (2)/src/gowin_ddr/gowin_ddr.v /home/quang1806/Desktop/ACG525_TEST/ch26_hdmi_color (2)/src/gowin_pllvr/gowin_pllvr.v /home/quang1806/Desktop/ACG525_TEST/ch26_hdmi_color (2)/src/hdmi_color.v /home/quang1806/Desktop/ACG525_TEST/ch26_hdmi_color (2)/src/vga/disp_driver.v /home/quang1806/Desktop/ACG525_TEST/ch26_hdmi_color (2)/src/vga/disp_parameter_cfg.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11 |
| Part Number | GW1NSR-LV4CQN48PC6/I5 |
| Device | GW1NSR-4C |
| Created Time | Thu Jun 26 10:23:46 2025 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | hdmi_color |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.095s, Elapsed time = 0h 0m 0.091s, Peak memory usage = 151.691MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.011s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 152.461MB Optimizing Phase 1: CPU time = 0h 0m 0.004s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 152.461MB Optimizing Phase 2: CPU time = 0h 0m 0.017s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 152.461MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.005s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 152.781MB Inferring Phase 1: CPU time = 0h 0m 0.003s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 152.781MB Inferring Phase 2: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 152.922MB Inferring Phase 3: CPU time = 0h 0m 0.004s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 152.922MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.052s, Elapsed time = 0h 0m 0.049s, Peak memory usage = 152.922MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.004s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 152.922MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.003s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 152.922MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.853s, Elapsed time = 0h 0m 0.868s, Peak memory usage = 184.633MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.076s, Elapsed time = 0h 0m 0.085s, Peak memory usage = 184.633MB Generate output files: CPU time = 0h 0m 0.056s, Elapsed time = 0h 0m 0.072s, Peak memory usage = 184.875MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 184.875MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 11 |
| I/O Buf | 11 |
| IBUF | 2 |
| OBUF | 9 |
| Register | 107 |
| DFF | 42 |
| DFFR | 20 |
| DFFC | 29 |
| DFFCE | 16 |
| LUT | 159 |
| LUT2 | 13 |
| LUT3 | 51 |
| LUT4 | 95 |
| ALU | 21 |
| ALU | 21 |
| INV | 14 |
| INV | 14 |
| IOLOGIC | 8 |
| ODDR | 8 |
| CLOCK | 2 |
| CLKDIV | 1 |
| PLLVR | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 194(173 LUT, 21 ALU) / 4608 | 5% |
| Register | 107 / 3573 | 3% |
| --Register as Latch | 0 / 3573 | 0% |
| --Register as FF | 107 / 3573 | 3% |
| BSRAM | 0 / 10 | 0% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk | Base | 37.037 | 27.000 | 0.000 | 18.519 | clk_ibuf/I | ||
| 2 | Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk | Generated | 6.006 | 166.500 | 0.000 | 3.003 | clk_ibuf/I | clk | Gowin_PLLVR_inst/pllvr_inst/CLKOUT |
| 3 | Gowin_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk | Generated | 6.006 | 166.500 | 0.000 | 3.003 | clk_ibuf/I | clk | Gowin_PLLVR_inst/pllvr_inst/CLKOUTP |
| 4 | Gowin_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk | Generated | 12.012 | 83.250 | 0.000 | 6.006 | clk_ibuf/I | clk | Gowin_PLLVR_inst/pllvr_inst/CLKOUTD |
| 5 | Gowin_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk | Generated | 18.018 | 55.500 | 0.000 | 9.009 | clk_ibuf/I | clk | Gowin_PLLVR_inst/pllvr_inst/CLKOUTD3 |
| 6 | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk | Generated | 30.030 | 33.300 | 0.000 | 15.015 | Gowin_PLLVR_inst/pllvr_inst/CLKOUT | Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk | u_div_5/clkdiv_inst/CLKOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk | 166.500(MHz) | 176.699(MHz) | 3 | TOP |
| 2 | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk | 33.300(MHz) | 71.234(MHz) | 7 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 0.347 |
| Data Arrival Time | 7.141 |
| Data Required Time | 7.488 |
| From | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_1_s0 |
| To | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_1_s0 |
| Launch Clk | Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk | |||
| 1.156 | 1.156 | tCL | RR | 50 | Gowin_PLLVR_inst/pllvr_inst/CLKOUT |
| 1.882 | 0.726 | tNET | RR | 1 | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_1_s0/CLK |
| 2.340 | 0.458 | tC2Q | RF | 6 | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_1_s0/Q |
| 3.300 | 0.960 | tNET | FF | 1 | u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/I1 |
| 4.399 | 1.099 | tINS | FF | 30 | u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/F |
| 5.359 | 0.960 | tNET | FF | 1 | u_dvi_encoder/serdes_4b_10to1_inst/n87_s0/I2 |
| 6.181 | 0.822 | tINS | FF | 1 | u_dvi_encoder/serdes_4b_10to1_inst/n87_s0/F |
| 7.141 | 0.960 | tNET | FF | 1 | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 6.006 | 0.000 | Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk | |||
| 7.162 | 1.156 | tCL | RR | 50 | Gowin_PLLVR_inst/pllvr_inst/CLKOUT |
| 7.888 | 0.726 | tNET | RR | 1 | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_1_s0/CLK |
| 7.488 | -0.400 | tSu | 1 | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 6.006 |
| Logic Level: | 3 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 1.921, 36.526%; route: 2.880, 54.759%; tC2Q: 0.458, 8.715% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 2
Path Summary:| Slack | 0.347 |
| Data Arrival Time | 7.141 |
| Data Required Time | 7.488 |
| From | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_1_s0 |
| To | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_2_s0 |
| Launch Clk | Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk | |||
| 1.156 | 1.156 | tCL | RR | 50 | Gowin_PLLVR_inst/pllvr_inst/CLKOUT |
| 1.882 | 0.726 | tNET | RR | 1 | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_1_s0/CLK |
| 2.340 | 0.458 | tC2Q | RF | 6 | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_1_s0/Q |
| 3.300 | 0.960 | tNET | FF | 1 | u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/I1 |
| 4.399 | 1.099 | tINS | FF | 30 | u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/F |
| 5.359 | 0.960 | tNET | FF | 1 | u_dvi_encoder/serdes_4b_10to1_inst/n86_s0/I2 |
| 6.181 | 0.822 | tINS | FF | 1 | u_dvi_encoder/serdes_4b_10to1_inst/n86_s0/F |
| 7.141 | 0.960 | tNET | FF | 1 | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_2_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 6.006 | 0.000 | Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk | |||
| 7.162 | 1.156 | tCL | RR | 50 | Gowin_PLLVR_inst/pllvr_inst/CLKOUT |
| 7.888 | 0.726 | tNET | RR | 1 | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_2_s0/CLK |
| 7.488 | -0.400 | tSu | 1 | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 6.006 |
| Logic Level: | 3 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 1.921, 36.526%; route: 2.880, 54.759%; tC2Q: 0.458, 8.715% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 3
Path Summary:| Slack | 0.347 |
| Data Arrival Time | 7.141 |
| Data Required Time | 7.488 |
| From | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_1_s0 |
| To | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_3_s0 |
| Launch Clk | Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk | |||
| 1.156 | 1.156 | tCL | RR | 50 | Gowin_PLLVR_inst/pllvr_inst/CLKOUT |
| 1.882 | 0.726 | tNET | RR | 1 | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_1_s0/CLK |
| 2.340 | 0.458 | tC2Q | RF | 6 | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_1_s0/Q |
| 3.300 | 0.960 | tNET | FF | 1 | u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/I1 |
| 4.399 | 1.099 | tINS | FF | 30 | u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/F |
| 5.359 | 0.960 | tNET | FF | 1 | u_dvi_encoder/serdes_4b_10to1_inst/n85_s0/I2 |
| 6.181 | 0.822 | tINS | FF | 1 | u_dvi_encoder/serdes_4b_10to1_inst/n85_s0/F |
| 7.141 | 0.960 | tNET | FF | 1 | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 6.006 | 0.000 | Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk | |||
| 7.162 | 1.156 | tCL | RR | 50 | Gowin_PLLVR_inst/pllvr_inst/CLKOUT |
| 7.888 | 0.726 | tNET | RR | 1 | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_3_s0/CLK |
| 7.488 | -0.400 | tSu | 1 | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 6.006 |
| Logic Level: | 3 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 1.921, 36.526%; route: 2.880, 54.759%; tC2Q: 0.458, 8.715% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 4
Path Summary:| Slack | 0.347 |
| Data Arrival Time | 7.141 |
| Data Required Time | 7.488 |
| From | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_1_s0 |
| To | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_1_s0 |
| Launch Clk | Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk | |||
| 1.156 | 1.156 | tCL | RR | 50 | Gowin_PLLVR_inst/pllvr_inst/CLKOUT |
| 1.882 | 0.726 | tNET | RR | 1 | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_1_s0/CLK |
| 2.340 | 0.458 | tC2Q | RF | 6 | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_1_s0/Q |
| 3.300 | 0.960 | tNET | FF | 1 | u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/I1 |
| 4.399 | 1.099 | tINS | FF | 30 | u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/F |
| 5.359 | 0.960 | tNET | FF | 1 | u_dvi_encoder/serdes_4b_10to1_inst/n82_s0/I2 |
| 6.181 | 0.822 | tINS | FF | 1 | u_dvi_encoder/serdes_4b_10to1_inst/n82_s0/F |
| 7.141 | 0.960 | tNET | FF | 1 | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 6.006 | 0.000 | Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk | |||
| 7.162 | 1.156 | tCL | RR | 50 | Gowin_PLLVR_inst/pllvr_inst/CLKOUT |
| 7.888 | 0.726 | tNET | RR | 1 | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_1_s0/CLK |
| 7.488 | -0.400 | tSu | 1 | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 6.006 |
| Logic Level: | 3 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 1.921, 36.526%; route: 2.880, 54.759%; tC2Q: 0.458, 8.715% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 5
Path Summary:| Slack | 0.347 |
| Data Arrival Time | 7.141 |
| Data Required Time | 7.488 |
| From | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_1_s0 |
| To | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_2_s0 |
| Launch Clk | Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk | |||
| 1.156 | 1.156 | tCL | RR | 50 | Gowin_PLLVR_inst/pllvr_inst/CLKOUT |
| 1.882 | 0.726 | tNET | RR | 1 | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_1_s0/CLK |
| 2.340 | 0.458 | tC2Q | RF | 6 | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_1_s0/Q |
| 3.300 | 0.960 | tNET | FF | 1 | u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/I1 |
| 4.399 | 1.099 | tINS | FF | 30 | u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/F |
| 5.359 | 0.960 | tNET | FF | 1 | u_dvi_encoder/serdes_4b_10to1_inst/n81_s0/I2 |
| 6.181 | 0.822 | tINS | FF | 1 | u_dvi_encoder/serdes_4b_10to1_inst/n81_s0/F |
| 7.141 | 0.960 | tNET | FF | 1 | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_2_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 6.006 | 0.000 | Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk | |||
| 7.162 | 1.156 | tCL | RR | 50 | Gowin_PLLVR_inst/pllvr_inst/CLKOUT |
| 7.888 | 0.726 | tNET | RR | 1 | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_2_s0/CLK |
| 7.488 | -0.400 | tSu | 1 | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 6.006 |
| Logic Level: | 3 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 1.921, 36.526%; route: 2.880, 54.759%; tC2Q: 0.458, 8.715% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |